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WM2636 12-bit Serial Input Voltage Output DAC with Internal Reference
Production Data, July 1999, Rev 1.0
FEATURES
* * * * * * * * 12-bit voltage output DAC Single supply from 2.7V to 5.5V DNL 0.5 LSBs, INL 2.0 LSBs Very low power consumption (3V supply): - 4.2mW, slow mode - 8.1mW, fast mode TMS320, (Q)SPI, and Microwire compatible serial interface Programmable settling time of 3.5s or 1s typical High impedance reference input buffer Power down mode 10nA
DESCRIPTION
The WM2636 is a 12-bit voltage output, resistor string digital-toanalogue converter that can be powered down under software control. Power down reduces current consumption to 10nA. An internal precision voltage reference is provided which can source up to 1mA. This can therefore be used as an external system reference. The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2636 is programmed with a 16-bit serial word comprising 4 control bits and 12 data bits. Excellent performance is delivered with a typical DNL of 0.5 LSBs. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain near rail-to-rail amplifier. The device is available in an 8-pin SOIC package. Commercial temperature (0 to 70C) and Industrial temperature (-40 to 85C) variants are supported.
APPLICATIONS
* * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation
ORDERING INFORMATION
DEVICE WM2636CD WM2636ID TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 8-pin SOIC 8-pin SOIC
BLOCK DIAGRAM
VDD (8) REFERENCE OUTPUT BUFFER WITH OUPUT ENABLE X1 1.024V/2.048V SELECTABLE REFERENCE
TYPICAL PERFORMANCE
1 VDD = 5V, VREF = External, Speed = Fast mode, Load = 10k/100pF 0.8 0.6 0.4
REF(6)
REFERENCE INPUT BUFFER X1 DAC OUTPUT BUFFER
DNL - LSB
X2 (7) OUT
2-BIT REFERENCE SELECT LATCH
0.2 0 -0.2 -0.4 -0.6 -0.8 -1
2-BIT CONTROL LATCH POWERDOWN/ SPEED CONTROL
DIN (1) SCLK (2) 16-BIT SHIFT REGISTER AND CONTROL LOGIC data
12-BIT DAC LATCH
NCS (3)
FS (4)
0
512
1024
1536
2048 DIGITAL CODE
2559
3071
3583
4095
POWER-ON RESET
WM2636
(5) AGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
1999 Wolfson Microelectronics Ltd.
WM2636
Production Data
PIN CONFIGURATION
DIN SCLK NCS FS 1 2 3 4 8 7 6 5 VDD OUT REF AGND
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 NAME DIN SCLK NCS FS AGND REF OUT VDD TYPE Digital input Digital input Digital input Digital input Supply Analogue I/O Analogue output Supply DESCRIPTION Serial data input. Serial clock input. Chip select. This pin is active low. Frame synchronisation for serial input data. Analogue ground. Analogue reference voltage input/output. DAC analogue output Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltage, VDD to AGND Digital input voltage Reference input voltage Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds WM2636CD WM2636ID -0.3V -0.3V 0C -40C -65C MIN MAX 7V VDD + 0.3V VDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF Load resistance Load capacitance Serial clock rate Operating free-air temperature SYMBOL VDD VIH VIL VREF RL CL FSCLK TA WM2636CD WM2636ID 0 -40 VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V See Note 2 10 100 20 70 85 TEST CONDITIONS MIN 2.7 2 0.8 VDD - 1.5 TYP MAX 5.5 UNIT V V V V k pF MHz C C
Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 2
WM2636
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH = VDD, VIL = 0V VDD = 5V, VREF = 2.048V Slow VDD = 5V, VREF = 2.048V Fast VDD = 3V, VREF = 1.024V Slow VDD = 3V, VREF = 1.024V Fast See Note 8 No load, all digital inputs 0V or VDD See Note 9 DAC code 128 to 4095, 10%-90% See Note 10 Slow Fast DAC code 128 to 4095 See Note 11 Slow Fast Code 2047 to 2048 SNR fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 12 71 1.6 2.9 1.4 2.7 1.9 3.4 mA mA mA mA 2k to 10k load See Note 7 0 VDD - 0.1 V % INL DNL ZCE GE DC PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 0.5 10 10 12 bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
2.0 0.5
4.0 1.0 20 0.6
LSB LSB mV % FSR mV/V ppm/C ppm/C
0.1
0.25
Power down supply current
0.01
10
A
Dynamic DAC Specifications Slew rate
2 14
V/s V/s
Settling time
Glitch energy Signal to noise ratio
3.5 1.0 10 75
s s nV-s dB
Signal to noise and distortion ratio Total harmonic distortion Spurious free dynamic range
SNRD THD SPFDR
59
66 -67 -59
dB dB dB
59
69
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PD Rev 1.0 July 1999 3
WM2636
Production Data
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Reference Configured as Input Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 VREF = 0.2VPP + 1.024V dc DAC code 2048 Slow Fast VREFOUTL VREFOUTH IREFSRC IREFSNK -1 100 -48 VDD > 4.75V 1.003 2.027 10 55 -65 M pF dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1.0 1.0 1.024 2.048 1.045 2.069 1
MHz MHz V V mA mA pF dB A A pF
Reference configured as output Low reference voltage High reference voltage Output source current Output sink current Load Capacitance PSRR Digital Inputs High level input current Low level input current Input capacitance IIH IIL CI Input voltage = VDD Input voltage = 0V 8 1 -1
Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs.
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PD Rev 1.0 July 1999 4
WM2636
Production Data
SERIAL INTERFACE
*
SCLK 1 tSUD DIN tSUCSFS NCS tWHFS FS tSUFS tSUC16FS D15 tHD D14 D13 D12 D1 D0 tSUC16CS 2 tWL tWH 3 4 5 15 16
Figure 1 Timing Diagram Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). SYMBOL tSUCSFS tSUFS tSUC16FS TEST CONDITIONS Setup time NCS low before negative FS edge. Setup time FS low before first negative SCLK edge. Setup time, sixteenth negative edge after FS low on which D0 is sampled before rising edge of FS. Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and the NCS rising edge. Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high. MIN 10 8 10 TYP MAX UNIT ns ns ns
tSUC16CS
10 25 25 8 5 20
ns ns ns ns ns ns
tWH tWL tSUD tHD tWHFS
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 5
WM2636
Production Data
TYPICAL PERFORMANCE GRAPHS
3 VDD = 5V, VREF = External 2.048V, Speed = Fast mode 2
1 INL - LSB
0
-1
-2
-3 0 512 1024 1536 2048 DIGITAL CODE 2559 3071 3583 4095
Figure 2 Integral Non-Linearity
3 VDD = 3V, VRF = 1V, Input Code = E
5 VDD = 5V, VREF = 2V, Input Code = 0 4.5
2.5 4
3.5 2 Output Voltage - V Output Voltage - V 3
.5 1
2.5
2
1 1.5
1 0.5 0.5
0 0 1 2 s I ink - mA 3 3.5
l ow S Fas t
0 4
0 0.5 1 1.5 2 2.5 3 3.5 Slow Fast 4
Isink - mA
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
4.135
2.071 VDD = 3V, VREF = 1V, Input Code = 4095 2.0705
VDD = 5V, VREF = 2V, Input Code = 4095
4.134
2.07
2.0695
4.133
Output Voltage - V
2.0685
Output Voltage - V
2.069
4.132
2.068
4.131
2.0675
2.067
4.13
2.0665
2.066 0 0.5 1 1.5 2 Isource - mA 2.5 3 3.5
Slow Fast
4.129
4
0
0.5
1
1.5
2 Isource - mA
2.5
3
3.5 Slow Fast
4
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 6
WM2636
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:
Output voltage = 2 VREF INPUT 1111 1111 1111
(
) CODE
4096
OUTPUT
2 VREF
(
) 4095
4096
1000
: 0000
: 0001
2 VREF
(
) 2049
4096
REF
1000
0000
0000
2 VREF
(
) 2048 = V
4096
0111
1111
1111
2 VREF
( (
) 2047
4096 1 4096
0000
: 0000
: 0001
2 VREF
)
0000
0000
0000
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
SERIAL INTERFACE
Explanation of data transfer: First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which updates the voltage output to the new level. The serial interface of the device can be used in two basic modes: * * four wire (with chip select) three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1 = 20MHz tWCH min+ tWCL min The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 12 bits limits the update rate for large input step transitions.
fSCLKmax =
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 7
WM2636
SOFTWARE CONFIGURATION OPTIONS
Production Data
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-bit data word. D15-D12 hold the programmable options. D15 D14 D13 D12 D11 D10 R1 SPD PWR R0 Table 2 Serial Word Format D9 D8 D7 D6 D5 D4 D3 D2 New DAC or control register value (12 bits) D1 D0
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 3.5s or 1s, typical to within 0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 1s, a ZERO defines a settling time of 3.5s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.
REGISTER ADDRESSING
A separate internal control register is available. This is accessed from the register access bits R1 (Bit D15) and R0 (Bit D12). R1 (BIT D15) 0 0 1 1 R0 (BIT D12) 0 1 0 1 Reserved Reserved Write data to control register REGISTER Write data to DAC
Table 3 Register Access Control The contents of the control register, shown below in Table 4, are used to program the internal reference function. D11 x D10 x D9 X D8 x D7 x D6 x D5 x D4 x D3 x D2 X D1 D0 REF1 REF0
Table 4 Control Register Contents
PROGRAMMABLE INTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10M and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 0 0 1 1 REF0) 0 1 0 1 External 1.024V 2.048V External REGISTER
Table 5 Programmable Internal Reference
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 8
WM2636
Examples: 1. Set internal reference voltage to 2.048V D6 x D5 x D4 x D3 x
Production Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 1 x 0 1 x x x x x 2. Write new DAC value and update DAC output D15 D14 D13 D12 D11 D10 0 x 0 0 D9 D8 D7
D2 x
D1 1
D0 0
D6 D5 D4 New DAC value
D3
D2
D1
D0
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 9
WM2636
Production Data
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body DM009.B
e
B
8
5
E
H
1
4
L
D h x 45o
A
A1 -C-
C
0.10 (0.004)
SEATING PLANE
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 o o 8 0
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 o o 0 8
JEDEC.95, MS-012
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999 10

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